A current reference circuit is an essential part of an autonomous Input/Output (I/O) limited integrated circuit. An approach to generate a stable current is to employ an external (e.g., off-chip) precision resistor and produce a fixed voltage across this resistor through internal (e.g., on-chip) circuitry. Off-chip resistors are used since on-chip resistors suffer from relatively large (e.g., 20-30%) tolerances and therefore are not very suitable for generating a stable reference current using this technique. In certain I/O-limited applications, current variations in a simplistic on-chip current reference circuit due to process voltage temperature (PVT) variations lead to specification violation or functional failure.
With complementary metal-oxide semiconductor (CMOS) processes in the deep submicron regime, second-order effects (e.g., drain-induced-barrier-lowering) have reduced transistors intrinsic drain-to-source resistance and have pushed transistors towards highly non-ideal current source behaviors. A temperature compensation technique includes generating a proportional to absolute temperature (PTAT) and a complementary to absolute temperature (CTAT) current and adding them up to achieve a smaller temperature coefficient. This, however, does not address process variations, which are especially problematic for deep submicron technologies.
Another technique to address temperature compensation is based on passively mixing components having opposite temperature and process coefficients. This approach, however, provides a very limited freedom as different components have different geometrical and structural issues. Also, this approach leads to further issues of reducing sensitivities without adding any extra fabrication or structural sensitivities.